1. Field of the Invention
This invention relates to an address generating circuit of a two-dimensional coding table, and particularly to an address generating circuit of a two-dimensional coding table where coded words are distributed in certain ranges of two events.
2. Description of the Related Art
For coding of time series signals having deviated generating frequency, unequal length codes which give a short code to a signal having a high occurrence frequency and a long code to a signal having a low occurrence frequency are used to allow compression coding. This coding is called an entropy coding (Huffman code is one type of the entropy coding). The entropy coding has been applied in various fields such as coding of voice signals and image signals.
In variable length coding and variable length decoding, the average code length can be minimized by coding to a bit length corresponding to a log (2 is the bottom) with respect to a reciprocal number of the appearance frequency of each code.
In particular, when the data occurrence probability is heavily deviated in making transmission or large accumulation of data, the entropy coding is effective for data compression. For example, in the case of recording daily wind direction for past 100 years, to record in a district having frequent northerly winds, it is advantageous to compress data when the wind directions and the coded words are corresponded as 1=north, 01=northeast, 001=south, 0001=west, etc. And in recording in a district having frequent westerly winds, data is advantageously compressed by assigning a short code to west. Similarly, in the case of recording daily wind velocity for past 100 years, it is possible to assign, for example, 1=10 m/sec, 01=30 m/sec, 001=5 m/sec, 0001=20 m/sec, etc. in order from high to low relating to the data occurrence probability.
In the above coding example, one-dimensional parameters such as wind direction and wind velocity were coded. Further, coding having two parameters (two-dimensional coding) can also be considered. For example, to record both the wind direction and wind velocity, with the wind direction and wind velocity as parameters, a short code is assigned in order from high to low relating to the occurrence probability. In this case, the codes are assigned as 1=north wind 10 m/sec, 01=south wind 10 m/sec, 10=south wind 10 m/sec, 001=west wind 10 m/sec, etc.
Generally, for entropy coding, assignment of the entropy codes becomes complex as the assembly of codes becomes larger. In particular, in the two-dimensional coding, the assembly of codes becomes a direct product of two assemblies of codes. To apply to this case, an escape code may be used for codes having sufficiently low occurrence probability.
The escape code takes a form having values of two codes (binary fixed length code) coupled with escape identification section as the entropy code. This escape code is defined, the entropy code is assigned to a combination of high occurrence probability, and the escape code is assigned to a combination of sufficiently low occurrence probability, so that the size of a coding table for fixing the corresponding relation between data and codes is small.
An example of the escape code in recording the aforementioned wind direction and wind velocity will be described. For example, the wind direction is coded using 4-bit codes as follows 0000=north, 0001=south, 0010=east, 0011=west, 0100=northeast, 0101=northwest, and the wind velocity is coded using 6-bit codes as follows: m/sec, 000001=20 m/sec, 000010=30 m/sec, 000011=40 m/sec, . . . for every 10 m/sec. And, these two codes are coupled into 10-bit codes indicating the wind direction using the high order 4 bits and the wind velocity using the low order 6 bits. Thus, a state with low occurrence possibility can be coded.
The coding table determining the corresponding relation between recorded data and codes is generally structured by assigning respective coded words to each address on memory. Therefore, to refer to a coded word corresponding to a certain data, the assigned address has to be determined. Particularly, in the two-dimensional coding table, an address in that coding table has to be calculated from the values of two events. A conventional address generating circuit to generate the address of such a two-dimensional coding table is as follows.
A first address generating circuit is a circuit to read from a coding table a coded word corresponding to the values of two events according to a software program. This address generating circuit has a CPU for processing a program and an instruction memory to store the program as essential components. In this address generating circuit, an address is generated as follows. First, an appropriate address is assigned on memory to every coded word corresponding to data. The program detects the values of two events and outputs an address corresponding to their parameters. For example, when recording the aforementioned wind direction and wind velocity, among the two events, the wind direction is determined to be event A and the wind velocity as event B, and an address of a coded word for north wind 10 m/sec is to be read. In this case, when event A=0001, event B=000001, and an address having a coded word stored in the coded word table is determined to be 0010 address, it is programed to read the 0010 address by a condition judgment of (A=0001) and (B=000001). Using the circuit thus programed, a condition is judged from the values of events A and B with respect to every coded word to generate an address of the coding table.
A second address generating circuit is a circuit to output an address of the coding table using hardware means such as a comparator or detector in which the values of two events are entered. Specifically, this is a process to generate an address of the coded word through hardware by preparing a dedicated decoder.
A third address generating circuit is a circuit having a coding table having the values themselves of two events corresponded to a coded word as an address. This address generating circuit has the value of event A as a high order of the address and the value of event B as a low order of the address, and the values of A and B are coupled to generate an address of the coding table. Such an address generating circuit does not need the addition of a dedicated hardware, and an address can be generated simply.
But, the aforementioned conventional address generating circuit of two-dimensional coding table has the following drawbacks.
The first address generating circuit according to program successively compares the values of two events on a program to output an address and requires the time for comparison. Therefore, it cannot be used for a high-speed processing such as a real time image processing. And, it also needs a system for address generation such as a CPU and an instruction memory for storing the program. Thus, the construction is complicated.
The second address generating circuit for generating an address through hardware needs a dedicated hardware for detecting an address of the coding table corresponding to the values of two events, so that the circuit becomes large when the circuit needs to correspond to a large volume of coded words exceeding 100 words.
The third address generating circuit with the coding table having the values of two events as an address has the drawback that a memory capacity which is required by a memory for storing a coding table becomes large.